Dry etching is an absolutely critical process in the fabrication of all micrometer and nanometer scale features on high-speed electronic and opto-electronic devices. In brief, the fabrication of such chips and devices involves the following process. A substrate of some semiconductor or metal is selected and a pattern is laid down over it, the pattern having open areas in it. The overlying structure containing the pattern is sometimes called a mask. Etching chemistry is then performed through the open areas, which means that in effect some of the underlying material exposed through the open areas is dissolved away so that the pattern is transferred into the underlying layer(s). Then, the mask is stripped away and what is left behind is the original substrate, but now the pattern has been transferred into it. The process is similar to silk screening or stamping a pattern into material. The resulting pattern has a three dimensional structure.
In the early days of integrated circuit fabrication, most etching was done using a wet chemical process that is quite similar to conventional photography. For example, to etch an array of grooves in a silicon wafer, the wafer is first placed in a high temperature, oxidizing environment and a layer of silicon dioxide is grown on the top surface of the wafer. Then, the oxidized wafer is covered with a thin photosensitive layer of gelatinous organic material called a “photoresist”. Next, a piece of material analogous to a photographic negative, called a “photomask”, is placed over the photoresist. Ultraviolet light is shined through openings in this photomask. The ultraviolet light changes the solubility of the photoresist. Thus, areas of photoresist that have been illuminated with the ultraviolet light display a different solubility than areas which have not been exposed to the light. Finally, a solvent is used which dissolves away only the areas of the photoresist, which have had their solubility increased by the ultraviolet light. At this point, the original pattern on the photomask has been transferred to the photoresist layer. Some people refer to this patterned photoresist layer as a “soft mask”.
Subsequently, a wet chemical, hydrofluoric acid (HF) dip is used to dissolve away the silicon dioxide, which has been exposed through each of the openings in the overlaying photoresist. Then, the photoresist is stripped off. At this point, it is apparent that the pattern originally appearing on the photomask has been transferred to the silicon dioxide layer overlying the silicon wafer. This patterned layer of silicon dioxide is sometimes referred to as a “hard mask”.
Finally, the wafer is dipped into a caustic etch, such as potassium hydroxide (KOH) which etches away the silicon exposed under the openings in the hard mask. After stripping away the hard mask, the desired silicon wafer with the etched grooves remains.
As an alternative to following the hard masking step described above with a KOH silicon etch, ion implantation or high temperature diffusion could optionally be used to place dopant atoms through the openings in the hard mask.
Many other structural and chemical variations using the sorts of wet processing steps described above are possible and are well known to those of skill in the art. In each case however, the corresponding process suffers from a problem that is inherent with the associated etching using wet chemicals. In particular, at the same time that the wet chemistry is etching down into the wafer, it is also etching laterally under the mask. Indeed, this undesired lateral etching tends to extend approximately as far as the desired vertical etching. This tendency for wet chemical etching to proceed equally in all directions without prejudice is called “isotropic etching”.
Isotropic etching is adequate for making a line that is 20 microns wide through a film that is 1 micron deep. The resulting inaccuracy in the edges of such a feature is a small percentage of the overall device structure; and therefore, it does not compromise performance. However, as smaller and smaller structures are fabricated, isotropic etching is inadequate. The industry is moving toward fabrication of structures with so called sub-micron features, which are essential for high speed computer chips, optical structures, and electronic and optoelectronic devices. In other words, the accurate transfer of a pattern, which is half a micron wide into a material, which is half a micron thick, requires absolutely straight vertical sidewalls, or anisotropic etching. Isotropic etching is inadequate because the associated rounded undercut would be a very high percentage of the active device material and would destroy its performance.
Presently, it is thought that the only way to get straight sidewalls is by a technique called reactive-ion etching (RIE). Rather than dipping the device in wet chemicals, it is exposed to reactive gases in plasmas. Energetic ions formed in the plasma are accelerated in the normal direction to the substrate where they enhance the etching chemistry at the bottom of the open area defined by the mask and not on the sidewalls. Thus, straight sidewalls can be achieved with reactive-ion etching.
Reactive-ion etching provides anisotropic etching. However, the ions are heavy ions like argon or CF3+ and are traveling at a few hundred electron volts of kinetic energy. Thus, they carry enough momentum to displace lattice atoms from their normal position. This damages the surfaces and often, the optical and electrical properties of the substrate have been detrimentally changed.
Fabrication of ultra small electronic and optoelectronic devices requires dry etching processes that give high anisotropy, high selectivity between different materials, and minimal surface damage. Currently, ion enhanced plasma etching processes (e.g. reactive ion etching (RIE) and electron cyclotron enhanced RIE (ECR)) create high aspect ratio nanometer scale features; however, etch induced damage has become increasingly troublesome as critical dimensions shrink. To minimize etch damage, reactive species generated in the plasma should have energies larger than the activation energy of the etch reaction (a fraction of an eV), but less than the energy required for atomic displacement (3 to 10 eV for III-V semiconductors). Given these limitations, the ion energies available in reactive-ion (about 300 eV) and electron cyclotron resonance plasma etching (about 50 eV) are not ideally suited for fabricating nanometer scale devices.
Placing the sample to be etched on the anode within a DC plasma environment is one way to ensure precise control over the anisotropic etching process while minimizing damage to the substrate and is described in commonly assigned U.S. Pat. No. 5,882,538, filed Aug. 28, 1996 and titled “METHOD AND APPARATUS FOR LOW ENERGY ELECTRON ENHANCED ETCHING OF SUBSTRATES”. This technique is called Low Energy Electron Enhanced Etching (LE4, for convenience), and operates by placing the etching substrate on the anode of a DC glow discharge. This method works well for conducting and semi-conducting substrates, but is inherently problematic for etching non-conducting substrates such as insulators because, in the aforementioned method, the substrate sample is physically and electrically connected to the anode in the plasma, thus becoming a conducting element of the electrical circuit within the plasma. An insulator, by definition does not efficiently conduct electrical current, therefore, placing an insulating substrate on the anode will impede the electrical flow and will be an inefficient and nearly impossible way to etch a non-conducting substrate.
What is needed and was apparently not available until the presently described invention, is a method of etching that eliminates the damage inflicted by reactive-ion etching, achieves anisotropic etching, and is indeed applicable to all forms of substrates, including insulating substrates. Furthermore, it is desirable to have additional control over the etching process. Specifically, it is desirable to have the ability to control more precisely the flux, or rate per unit area of particles being imparted to the sample, and the energy that the particles impart.
A method of electron-impact-induced anisotropic etching of silicon (Si) by hydrogen is discussed in a 1982 article by S. Vepcek and F.-A. Sarott, “Electron-Impact-Induced Anisotropic Etching of Silicon by Hydrogen”, Plasma Chemistry and Plasma Processing, Vol. 2, No. 3, p. 233. The authors discuss successful etch rates of up to 1,000 Å/min with little surface roughness at low temperatures. At higher temperatures a rougher pattern was seen. While their exact methodology is unclear, the authors apparently used an apparatus described in a previous publication by A. P. Webb and S. Vepcek, “Reactivity of Solid Silicon With Hydrogen Under Conditions of a Low Pressure Plasma”, Chemical Physics Letters, Vol. 62, No. 1, p. 173 (1978). That publication describes an apparatus including a DC glow discharge device with the sample immersed in the positive column. The cathode was a standard hot cathode (heated to between 1500-2000 K) having a tungsten filament coated with thorium oxide. While this technique apparently worked for etching Si(111) with hydrogen, it would not work using other reactive gases such as oxygen, chlorine, and fluorine because the hot filament would be immediately consumed. Furthermore, the apparatus described by Vepcek and Sarott is cumbersome.
Other experiments, reported by Gillis et al. in an article entitled “Low-Energy Electron Beam Enhanced Etching of Si(100)-(2×1) by Molecular Hydrogen,” J. Vac. Sci. Technology B 10(6), November/December, p. 2729 (1992), focused on flooding Si with low energy electrons (200-1000 eV) produced by an electron gun. The authors reported etching at a rate of about 100 Å/min with low damage to the Si surface. Other papers by the present inventors are: “Low Energy Electron—Enhanced Etching of Si(100) in Hydrogen/Helium Direct—Current Plasma”, (Gillis et al., Appl. Phys. Lett., Vol 66(19), p. 2475 (1995)); “Low Energy Electron—Enhanced Etching of GaAs(100) in a Chlorine/Hydrogen DC Plasma” (Gillis et al., Appl. Phys. Lett., Vol. 68(16), p. 2255 (1996)); “Low Energy Electron-Enhanced Etching of GaN in a Hydrogen DC Plasma” J. Electrochem. Soc., 143, L251 (1996); and “Highly Anisotropic, Ultra-smooth Patterning of GaN/SuiC by Low Energy Electron Enhanced Etching in a DC Plasma” (Gillis et al., J. Electr. Mat. 26, 301-305 (1997)). These publications are incorporated herein by reference, in their entireties.
H. Watanabe and S. Matsui, writing in Applied Physics Letters, Volume 61, 1992, pp. 3011-3013, describe a related approach to achieve a process they call Electron Beam (EB)-assisted dry etching. They use porous grids to extract a “shower” of electrons from an ECR plasma and direct it toward a substrate. However, they operate the ECR source on argon gas, and then insert a separate gas ring nozzle between extraction grids and substrate. This gas ring, resembling somewhat an ordinary gas burner on a kitchen range, distributes the reactive gas (chlorine, in their case) over the etching substrate. They apply only a DC bias to the substrate, to increase electron collection efficiency and energy. They report results only for semiconductor substrates, not insulators.